With a progress in the technology of die manufacturing and packaging, three-dimensional integrated circuits (3DICs) have been developed in which two or more dies are integrated vertically and/or horizontally in a single die stack. Depending on the functional requirement, each stacked die includes a PLL to generate an individual clock. The frequencies of the clocks in each of the stacked dies therefore vary. Further, existing PLLs generally occupy a large die area and therefore increase the total die area of each stacked die.